• 4-issue RISC architecture

• 9-stage pipeline

• Super scalar

• 32KB data CACHE

• 32KB instruction CACHE

• 256KB L2 CACHE

• 512KB byte SRAM

• 1MB byte FLASH

• Voltage detection unit

• Frequency detection unit

• Temperature detection unit

• Power supply burr detection unit

• Light detection unit

• Physical detection protection

• Unique serial number for each product

• Power domain: 0.8V 1.8V, 3.3V

• Commercial grade operating temperature：0-70 degrees

• Industrial grade operating temperature：-40~85 degrees

• Boot Rom: Secure boot, authenticated encryption protection for user code

• Security debugging control: configurable debugging interface for open and close

• Access control unit: authorized access control to address space

• Security Monitor: all security information be monitored and collected in real time

• A random root key in side to encrypt and protect the application system key

• Symmetric algorithms: SM4/AES/DES/3DES

• Asymmetric algorithms: SM2/ SM9/RSA1024/RSA204

• Hashing algorithms: SM3/SHA1/SHA256/SHA384/SHA512/HMAC

• Hardware algorithm engine independent of CPU

• Protection from non-authorized access of data stored in non-volatile memory and for data integrity

• True random number generator, internal multi-channel physical random source, CPU and algorithm engine can be independently running.

• Level I of security chip for commercial crypto product certification